Integrated circuits are manufactured by a highly complex and costly manufacturing process. During the first stages of this process a wafer is formed. A wafer includes multiple dice that are parallel to each other and are arranged in an ordered array.
FIG. 1 illustrates rectangular-shaped dice that are arranged in columns and rows and are separated by scribe lines. The wafer 11 is characterized by a die X-axis pitch 26 and a die Y-axis pitch 28. Referring to FIG. 1, wafer 11 includes multiple dice 12(0,0)-12(k,j) that are collectively denoted 12. FIG. 1 also illustrates a global coordinate system 20 that includes X-axis 22 and Y-axis 24. The dice are arranged in parallel to these imaginary axes and are aligned with global coordinate system 20.
Wafers are inspected for defects. The inspection can involve comparing between a die and a reference die. The following patents, all being incorporated herein by reference, illustrate various wafer inspection devices and methods as well as registration and alignment methods: U.S. Pat. No. 5,610,102 of Gardopee et al., U.S. Pat. No. 6,021,380 of Fredriksen et al., U.S. Pat. No. 6,937,753 of O'Dell et al., and U.S. Pat. No. 6,324,298 of O'Dell et al., and U.S. Pat. No. 4,981,529 of Tsujita.
In various wafer inspection systems the image processing is applied “off-line”. Typically, multiple frames that cover a die are acquired, the location of the die is provided to a scanner that in turn adjusts the scanning pattern such as to align the acquired frames with the dice, and after the scanning process is completed a die to die comparison is preformed.
There is a need to provide an efficient inspection system that can inspect wafers and a method for inspecting wafers.